Data converter standards
The JESD204/JESD204B revision data converter serial interface standard was created by the JEDEC committee to standardize and reduce the number of data I/Os between high-speed data converters and other devices such as field programmable gate arrays (FPGAs).
The JESD204B supports the high bandwidth required by the current generation of high-performance, high-speed, multi-channel applications while significantly reducing the number of digital I/O required. For example, many high-speed analog-to-digital converters that previously required a complex interface design of multiple FPGA I/Os now perform the same task with just a few pins. The overall bandwidth of the interface can also be divided into multiple channels based on application requirements, but without requiring additional pins.
Fewer connections simplify the layout and allow a smaller form factor to be implemented without impacting overall system performance, according to Analog Devices Inc. (ADI) in Norwood, Massachusetts. These attributes are important to address system size and cost constraints for a range of high-speed A/D converter applications, including wireless infrastructure, transceiver architectures, software-defined radios, portable instruments, medical ultrasound equipment, and aerospace applications, such as radar and secure communications.
There have been incremental improvements and innovations in the move to advanced SoCs. Programmable logic with embedded processors started appearing about 10 years ago. Dedicated processors had ARM and DSP accelerators, but they were not as flexible as programmable logic. Langlois says the race really took off around 2004-2005, when traditional FPGAs became more of a software engine and began to compete with existing products.
The next big milestone for Xilinx was the Zynq, which was marketed as an SoC rather than an FPGA. It came to the fore about four years ago when the combination of software, hardware and multiple peripherals began to emerge.
Parallel signal processing
“The next step is what to do with all this data,” adds Avnet’s Langlois. “Over 200 gigabytes of bandwidth requires a lot of processing power to retrieve data. You need massively parallel signal processing, which we introduce with embedded processors like Xilinx’s Zynq Ultrascale+ MPSoC [multiprocessor SoC]a real SoC with all the programmable logic, but also a 64-bit quad-core ARM A53 processor system, built-in memory, security features, more gigabit receivers and signal processing in one device. This is our flagship, just now rolling out, like the first devices will be delivered this summer.”
This new generation of SoCs offers numerous benefits to the end user: much higher performance, faster design-to-market cycles, the ability to use years of legacy software, and more. However, it also necessitates more software expertise on the part of designers, especially as end users increasingly demand pre-engineered solutions rather than trying to build their own solutions from scratch as SoC complexity becomes more high and higher with each new version. It’s all part of an effort to avoid commercial smartphone obsolescence, where buying a phone more than a year old can be several generations behind in technology and software.
“Software infrastructure will now dominate the entire development landscape and, by extension, all the functionality a user can get,” says Langlois. “For example, many of our military customers are designing products that not only want to be able to communicate, like SDRs, but also send video, sometimes from multiple camera streams, over the air securely. This was a big challenge because you don’t have enough bandwidth to send raw video. However, the latest generation can compress this video within the SoC using H.265 high-efficiency video encoding, making it possible to send streaming video from UAVs.”
Several trends have forced the evolution of system architectures, in turn driving the evolution of the required buses, according to a white paper by SoC specialist Arteris Inc. in Campbell, California. The first trend involves application convergence, “the mixing of different types of traffic in the same SoC design (video, communication, computing, etc.),” states the Arteris white paper. “These types of traffic, although very different in nature, for example from a quality of service perspective, now have to share resources that were supposed to be “private” and hand-crafted for the specific traffic in previous projects.
“Moore’s Law is driving the integration of many IP blocks on a single chip. It is a means of application convergence, but it also enables entirely new approaches – parallel processing on a chip using very small processors – or simply allowing SoCs to handle more data streams, such as communication channels,” according to the white paper. “The consequences of intergenerational silicon process evolution: Gates cost relatively less than cables, both in terms of area and performance, than a few years ago.
“Time-to-market pressures drive most projects to make heavy use of synthesizable RTL [register transfer levels] instead of manual layout, which in turn limits the choice of available implementation solutions to fit a bus architecture into a design flow,” the white paper says.
This leaves SoC manufacturers in a bit of a quandary: trying to keep up with extremely fast-moving and evolving technology and use it to meet increasingly complex military requirements, while remaining aware of the realities of military procurement and life cycles.
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